Active Matrix Arrays
Large modern flat panel displays are active matrix (AM) arrays that solve the problem of creating a 2D scene (frame by frame) from signals that are fed in only from the edges of the panel. Data lines run vertically feeding pixels along each column while scan lines run horizontally feeding pixels along each row. A pixel along a column receives its brightness information from the data line, but through a switching transistor whose gate is addressed by the scan line for that pixel’s row. The switching transistors are for the most part kept in their off state except for a brief pulse, once per display refresh cycle, during which time the data line voltage is passed to the pixel, updating its brightness information. By sequentially addressing the scan lines while simultaneously updating the data line voltages (along all columns, simultaneously) the scene frame is set over the entire 2D array.
In an AM-LCD panel that data line voltage resets the metastable orientation of a liquid crystal (LC) which then allows more or less of the backlight through the crossed polarizers to the viewer. The thin film switching transistors (Sw-TFTs) used in this application need not pass high currents so relatively low mobility amorphous Si can be used in the transistor channel. In addition to the Sw-TFT a storage capacitor (in parallel to the LC) is typically included within each pixel to sustain the voltage written to the LC throughout the refresh cycle. The Sw-TFT and the capacitor comprise the AM-LCD backplane (1T+1C) circuit. Note that the energy for the light in AM-LCD comes from a separate power supply driving the backlight.
AMOLED uses a similar active matrix addressing scheme but requires at least one additional (drive) transistor in the so called 2T+1C backplane circuit. For an OLED the current level through it sets its brightness. That current is sourced to the OLED from a separate power line through the drive transistor (D-TFT) with the current level controlled by the voltage applied to the D-TFT’s gate. That D-TFT’s gate voltage comes from the data line, through the Sw-TFT, whenever the corresponding scan line is addressed (with the storage capacitor wired in parallel to the D-TFT’s gate, sustaining its voltage throughout the refresh cycle).